Race Around Condition in J-K Flip-Flop

In this post on J-K Flip-Flop, we will study the Race Around Condition in a clocked (level-triggered) JK flip-flop. But before that, we will study the Logic symbol, truth table, operation of Positive-edge triggered J-K flip-flop and the J-K Excitation Table or J-K Transition Table. Finally, we will know about 7476 TTL IC (a J-K flip-flop based IC).


Logic symbol & truth table of Positive-edge triggered J-K flip-flop

The J-K flip-flop has the features of all the other types of flip-flops. The logic symbol for the positive-edge triggered J-K flip-flop is illustrated in Fig.1.1(a). The inputs labeled J and K are the data inputs. The input labeled CLK is the clock input. Outputs Q and Q’ are the usual normal and complementary outputs on a flip-flop.

A truth table for the J-K flip-flop is shown in Fig.1.1(b).


Figure 1.1 Positive-edge triggered J-K flip-flop (a) Logic symbol (b) Truth table

When the J and K inputs are both 0, the flip-flop is in the hold mode. In the hold mode, the data inputs have no effect on the outputs.

The outputs “hold” the last data present. Lines 2 and 3 of the truth table show the reset and set conditions for the Q output. Line 4 illustrates the useful toggle position of the J-K flip-flop.

When both data inputs J and K are at 1, repeated clock pulses cause the output to turn off-on-off-on-off-on, and so forth. This OFF-ON action is like a toggle switch and is called toggling.

Operation of the Positive-edge triggered J-K flip-flop

The basic operation of a positive edge-triggered J-K flip-flop is illustrated in Figure1.2

The J and K inputs of the J-K flip-flop are synchronous inputs because data on these inputs are transferred to the flip-flop’s output only on the triggering edge of the clock pulse.

When J is HIGH and K is LOW, the Q output goes HIGH on the triggering edge of the clock pulse, and the flip-flop is SET.

When J is LOW and K is HIGH, the Q output goes LOW on the triggering edge of the clock pulse, and the flip-flop is RESET.

When both J and K are LOW, the output does not change from its prior state. This is called no change state(NC).

When J and K are both HIGH, the flip-flop changes state. This is called the toggle mode.


Figure 1.2 Operation of a positive edge-triggered J-K flip-flop.

Remember, the flip-flop cannot change state except on the triggering edge of a clock pulse. The J and K inputs can be changed at any time when the clock input is LOW or HIGH (except for a very short interval around the triggering transition of the clock) without affecting the output.

We must review the operation of the J-K flip-flop using a different approach, one called an excitation table or transition table.

J-K Excitation Table or J-K Transition Table

Here is the operation of the J-K flip-flop using a different approach, one called an excitation table (Table 1). The leftmost column of this table lists each possible FF output transition.

This column list the FF’s PRESENT state, symbolized as QN, and the NEXT state, symbolized as QN+1, for each transition. The last column list the J and K levels required to produce each transition. Let’s examine each case.


Table 1: J-K Excitation Table OR J-K Transition Table

The operation of the J-K flip-flop using the Transition table is explained below:

0 to 0 transition: The FF PRESENT state is at 0 and is to remain at 0 when a clock pulse is applied. From our understanding of how a J-K flip-flop works, this can happen when either J = K = 0 (no-change condition) or J = 0 and K = 1 (clear condition). Thus, J must be at 0, but K can be at either level. The table indicates this with a “0” under J and an “x” under K. Recall that “x” means the don’t-care condition.

0 to 1 transition: The PRESENT state is 0 and is to change to a 1, which can happen when either J = 1 and K = 0 (set condition) or J = K = 1 (toggle condition). Thus, J must be a 1, but K can be at either level for this transition to occur.

1 to 0 transition: The PRESENT state is 1 and is to change to a 0, which can happen when either J = 0 and K = 1 or J = K = 1. Thus, K must be a 1, but J can be at either level.

1 to 1 transition: The PRESENT state is a 1 and is to remain a 1, which can happen when either J = K = 0 or J = 1 and K = 0. Thus, K must be a 0 while J can be at either level.

The use of this J-K transition table (Table 1) is a principal part of the synchronous counter design procedure.

Race-around Condition in a clocked JK flip-flop (level triggered J-K flip-flop)

The Race-around Condition is a major problem in clocked J-K flip-flop.

The truth table of J-K flip-flop shows that when both data inputs J and K are at 1, and CLK=1 the output toggles.

Consider the input J=1 and K=1 and output Q=0; after the propagation delay of flip-flop, the output will change from 0 to 1. Since in a J-K flip-flop, the output is connected to inputs, this output act as input, and after the next propagation delay, the output will change from 1 to 0. This process is continued and at the end of the applied clock pulse, the output is uncertain. This situation is known as the Race-around Condition.

This uncertainty of output can be avoided if the propagation delay time of flip-flop (∆ t) is increased. The propagation delay time of the flip-flop (∆ t) must be greater than the duration of the clock pulse(T) or the duration of the applied clock pulse(T)gets reduced and it becomes less than the propagation delay time of the flip-flop (∆ t). This is a restrictive requirement since the operation of the circuit depends on the width of the clock pulse.

Increasing the delay of the flip-flop is not a good solution. By increasing the delay, the speed of the system is decreased. It is also difficult to reduce the width of the applied pulse beyond the delay of flip-flop because the propagation delay time of flip-flop (∆ t) is in nanoseconds.

Therefore the most practical solution to avoid the problem of Race-around Condition is

  1. to use the clocked J-K flip-flop in Master-and-Slave mode or
  1. to use edge triggered J-K flip-flops means the output of flip-flops should respond, when the clock changes state.

7476 TTL – a commercially used J-K flip-flop based IC

7476 TTL is a commercially used J-K flip-flop based IC. The logic symbol for the commercial 7476 TTL J-K flip-flop is shown in Fig.2(a).

Added to the symbol are two asynchronous inputs (preset and clear). The synchronous inputs are the J and K data and clock inputs. The customary normal (Q) and complementary (Q’) outputs are also shown.

A detailed truth table for the commercial 7476 J-K flip-flops is drawn in Fig. 2(b).


Figure 2. (a) Logic symbol for Commercial J-K flip-flop
(b)Truth table for 7476 J-K flip-flop

Here the asynchronous inputs (such as PS and CLR) override synchronous inputs. The asynchronous inputs are activated in the first three lines of the truth table. The synchronous inputs are irrelevant (overridden) in the first three lines in Fig. 2(b); therefore, an X is placed under the J, K, and CLK inputs for these rows. The prohibited state occurs when both asynchronous inputs are activated at the same time. The prohibited state is not useful and should be avoided.

When both asynchronous inputs (PS and CLR) are disabled with a 1, the synchronous inputs can be activated. The bottom four lines of the truth table in Fig. 2(b) detail the hold, reset, set, and toggle modes of operation for the 7476 J-K flip-flop.

Uses of J-K flip-flops: J-K flip-flops are used in many digital circuits. You will use the J-K flip-flop, especially in counters. Counters are found in almost every digital system.

Summary:

In summary, the J-K flip-flop is considered the “universal” flip-flop. Its unique feature is the toggle mode of operation so useful in designing counters. When the J-K flip-flop is wired for use only in the toggle mode, it is commonly called a T flip-flop. J-K flip-flops are available in both TTL and CMOS IC forms. Typical CMOS

J-K flip-flops are the 74HC76, 74AC109, and 4027 ICs. The original 7476 J-K flip-flop has recently become obsolete and has been replaced by newer versions. This IC is the foundation for JK flip-flops. The description of the original 7476 IC is included as it provides a clear understanding of how JK flip-flops work.

Related Posts

JK Flip-flop – operation, truth table, excitation table

Asynchronous inputs in Flip-Flops

Author of this post

This post is co-authored by Professor Saraswati Saha, who is an assistant professor at RCCIIT, a renowned degree engineering college in India. Professor Saha teaches subjects related to digital electronics & microprocessors.

Race Around Condition in J-K Flip-Flop
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