Microprocessor MCQ 8085 & 8086 – Part 3
Last updated on April 30th, 2023 at 04:41 pm
This is part 3 of the Microprocessor MCQ (Multiple Choice Questions) on 8085 & 8086.
This page contains question number 17 to question number 24 [out of 40 questions of this set].
Follow the links given below to find the other 4 parts of this MCQ set containing microprocessor 8085 MCQ and microprocessor 8086 MCQ.
MCQ Part 1 | MCQ Part 2 | MCQ Part 4 | MCQ part 5
Microprocessor MCQ on 8085 & 8086 – part 3
17] In 8085 the addressable memory is
a] 64kB
b] 1MB
c] 4kB
d] 16kB
18] SP (stack pointer) register holds the
a] Base address of stack
b] Address of stack top
c] Address of the instruction to be fetched
d] None of these
19] MOV A, M is executed by
a] 1 machine cycle
b] 3 machine cycle
c] 4 machine cycle
d] 2 machine cycle
20] When PUSH instruction is executed, the stack pointer register is
a] decremented by two
b] incremented by two
c] decremented by one
d] incremented by one
21] The program counter(PC) in a microprocessor
a] keeps the address of the next instruction to be fetched
b] counts the number of instructions being executed on the microprocessor
c] counts the number of program being executed on the microprocessor
d] counts the number of interrupts handled by the microprocessor
22] The BSR mode in 8255 is used with one of the following
a] port A
b] port B
c] port C
d] none of these
23] what are the conditions that BIU can suspend fetching instruction?
a] current instruction requires access to memory or I/O port
b] a transfer control (jump or call) instruction occurs
c] transfer queue is full
d] none of these
24] Machine cycles in “CALL” instruction are
a] 6
b] 5
c] 4
d] 3
