Microprocessor MCQ on 8085 & 8086 – Part 5
Last updated on April 30th, 2023 at 04:44 pm
This is part 5 of the Microprocessor MCQ (Multiple Choice Questions) on 8085 & 8086.
This page contains question number 33 to question number 40 [out of 40 questions of this set].
Follow the links given below to find the other 4 parts of this MCQ set containing microprocessor 8085 MCQ and microprocessor 8086 MCQ.
MCQ Part 1 | MCQ Part 2 | MCQ Part 3 | MCQ Part 4
Microprocessor MCQ on 8085 & 8086 – part 5
33] The stack and stack pointer
a] both reside in memory
b] both reside in the CPU
c] former reside in memory and the later in CPU
d] none of these
34] The addressing mode of the instruction LDAX B is
a] direct
b] register indirect
c] implicit
d] immediate
35] The instruction PCHL
a] stores the content of the HL pair to a specified memory location
b] copies the content of the HL pair to the program counter
c] stores the content of the HL pair to the accumulator
d] exchanges the content of the HL pair with the program counter
36] Which of the following signals indicates an 8-data transfer from odd address bank?
a] A0=0 and BHE=0
b] A0=1 and BHE=1
c] A0=0 and BHE=1
d] A0=1and BHE=0
37] A single instruction to clear the higher four bits of the accumulator in 8085 microprocessor is
a] XRI 0FH
b] ANI F0H
c] ANI 0FH
d] XRI F0H
38] Which one of the following is not a NON-Maskable interrupt of 8085 microprocessor?
a] TRAP
b] INTR
c] RST 7.5
d] RST 3
39] Length of physical address in 8086 is
a] 16 bit
b] 4 bit
c] 24 bit
d] 20 bit
40] The 8051 microcontroller has
a] 128 bytes on chip RAM
b] 8 K bytes on chip ROM
c] 16 K bytes on chip RAM
d] 32 K bytes on chip ROM
