8086 Microprocessor Architecture – class notes with pdf download

Last updated on March 4th, 2022 at 05:22 pm

Before we start our lessons in 8086 microprocessor architecture, let’s quickly talk about what is new in it.

In case of 8085 microprocessor, the processor first fetches the instruction byte from memory. Then the instruction decoder decodes it. Finally, the microprocessor performs a particular task according to the instruction.

So the sequence of operation is as follows:    Fetching –> decoding –> execution

But in the case of 8086, if you see the block diagram of the architecture, you will find that the whole architecture is divided into two major parts:  
           (1) Bus Interface Unit (BIU) and 
           (2) Execution Unit (EU)

BIU fetches the instruction byte with the help of address bus and data bus and stores the bytes in an instruction queue register which is FIFO in nature.

The EU unit gets the byte or code from the queue and then decodes and executes it. 

To do this EU does not require address bus. When BIU fetches the next instruction byte from memory then the EU executes the prefetched code from the queue. So both BIU and EU work in parallel. This parallel processing of BIU and EU speeds up the processing.

Here you will be able to read the content of this class notes in 8086 microprocessor architecture as an embedded pdf. Also, you can download it from the given link.

8086 Microprocessor – Architecture – pdf online

Note: it may take a few seconds to load the embedded pdf.

8086-mp-architecture-cover-page-merged

Download link of pdf notes

Go to Microprocessor Home Page